In large scale integration, electrical devices such as complementary metal-oxide semiconductor (CMOS) circuitry are fabricated in large quantities on substrates. These substrates can be bonded together using microfabrication techniques to efficiently manufacture micromachined structures. The term “semiconductor substrate” includes semiconductive material. The term is not limited to bulk semiconductive material, such as a silicon wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term “substrate” refers to any supporting structure including but not limited to the semiconductor substrates described above. A substrate may be made of silicon, glass, gallium arsenide, silicon on sapphire (SOS), epitaxial formations, germanium, germanium silicon, diamond, silicon on insulator (SOI) material, selective implantation of oxygen (SIMOX) substrates, and/or like substrate materials. The substrate can be made of silicon, which is typically single crystalline.
In many applications, the substrates being bonded together can be semiconductor substrates such as silicon wafers. In wafer bonding, two or more wafers are bonded together. Each wafer can have a plurality of electrical devices formed thereon prior to the wafer bonding process. The bonding process can be used, although need not be used, to form a controlled environment, such as a hermetic seal, between the bonded adjacent wafers. Electrical interconnections can be made between the wafers. After the wafers are bonded together, saw/dice, wire bond and final package processes can be performed, as are conventional. Typical singulated die can be MicroElectroMechanical Systems (MEMS), such as field emitter display devices, accelerometers, bolometers, mirror arrays, optical switches, pressure gauges, memory storage devices such as atomic resolution storage devices, turbine chambers, and combustion chambers.
Packaging bonded wafers is a cost savings over packaging individual die. Due to the high costs of die-level packaging, wafer-level packaging is viewed as important for MEMS products. MEMS devices that are fabricated in wafer-level packaging can include such aspects as electrical interconnections between wafers and a fixed gap spacing distance between adjacent wafers. Optionally, a hermetic or gas impervious seal can also be formed to maintain a specific environment such as a vacuum, a specific gas, or protection from gases that are in the ambient or external environment. These aspects can be significant for MEMS such as atomic resolution storage devices, field emitter displays, or other highly integrated components made on multiple wafers. It would be an advantage in the art to develop electrical device fabrication processes that form a fixed gap spacing distance between adjacent wafers while minimizing the number of process steps so as to result in low cost and high yields.